examples/stream_test.c: what pins sampled?

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examples/stream_test.c: what pins sampled?

Andrey Gursky
Dear libftdi developers and users,

I believe one can use examples/stream_test.c [1] as an example how to
exploit the ft2232h as an up to 60 MHz logic analyzer. Could you
clarify, what pins exactly are sampled, e.g. only AD0..AD7? It would
be nice, if you could also add this info into the source code.

[1] http://developer.intra2net.com/git/?p=libftdi;a=blob;f=examples/stream_test.c;h=43abea9506c1d93b175c86600dbe1c641a1bcf44;hb=HEAD

Thanks,
Andrey

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Re: examples/stream_test.c: what pins sampled?

Uwe Bonnes
>>>>> "Andrey" == Andrey Gursky <[hidden email]> writes:

    Andrey> Dear libftdi developers and users, I believe one can use
    Andrey> examples/stream_test.c [1] as an example how to exploit the
    Andrey> ft2232h as an up to 60 MHz logic analyzer. Could you clarify,
    Andrey> what pins exactly are sampled, e.g. only AD0..AD7? It would be
    Andrey> nice, if you could also add this info into the source code.

The final clarification is the datasheet. Have a look at it.

FT2232H synchronous FIFO mode will always sample a 60 MHz (CLKOUT
frequency). Probably the RX buffer will soon be full, RXF will assert and
sampling will stop until the RX buffer has been transfered to the host. Than
sampling will restart, signaled by RXF. This will give no sensible sampling
for a logic analyser. Toggling RD_N in a 1:2 or 1:3 or higher ratio with
regard to clkout could sample at a lower frequency. Data rate of 20 MByte/s
in the 1:3 case should be substainable on a fast PC. Data rate of 30 MByte/s
in the 1:2 is ambigious especially without the availability of deeper
buffers.

Setting the sampling ratio of CLKOUT to sampling frequency would require
some signaling. Perhaps a synchronous fifo write cycle to some
programmable divider could set the ratio.

But all this needs substantial external logic, making the approach less
attractive.

Bye
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Uwe Bonnes                [hidden email]

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--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

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Re: examples/stream_test.c: what pins sampled?

Rodney Sinclair
Andrey,

60 MHz is the clock rate.  At 8 bits per clock, this would appear to be
the 480 Mb/sec USB 2.0 data rate, but, because of the bit packing, the
maximum realizable data rate is really about 53 MB/sec (personal
experience and other reports).  The chips include a "data enable" or
similar to gate the incoming data based on the bus availability,
serialized data rate, etc.

Rodney

On 04/29/2015 09:41 AM, Uwe Bonnes wrote:
>      Andrey> Dear libftdi developers and users, I believe one can use
>      Andrey> examples/stream_test.c [1] as an example how to exploit the
>      Andrey> ft2232h as an up to 60 MHz logic analyzer. Could you clarify,
>      Andrey> what pins exactly are sampled, e.g. only AD0..AD7? It would be
>      Andrey> nice, if you could also add this info into the source code.
>


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